1. Field of the Invention
The present invention is related to a pixel set, and in particular, to a pixel set having a design of capacitance compensation.
2. Description of Related Art
Generally, an active matrix liquid crystal display (AM-LCD) mainly includes an active device array, a color filter and a liquid crystal layer. FIG. 1 is a schematic top view of a conventional active device array. Referring to FIG. 1, an active device array 100 mainly includes a plurality of pixels 110 arranged to form an array. Each of pixels 110 comprises a scan line 112, a data line 114, an active device 116 and a pixel electrode 118 corresponding to the active device 116.
It is noted that two adjacent pixels 110 share one data line 114 in the active device array 100 for saving the amount of the data lines 114 so as to reduce the loading of the driving chips or the amount of the driving chips. That is to say, the pixels 110 of the active device array 100 are configured in pairs. Simultaneously, a storage capacitance electrode 120 is further disposed in the pixel 110 for stabilizing the display frame of the liquid crystal display. Moreover, the active device 116 can be directly disposed on the scan line 112 for enlarging the disposition area of the pixel electrode 118, that is to say, the scan line 112 and the active device 116 share the same space.
FIG. 2 is an equivalent circuit diagram of a liquid crystal display (LCD) applying the active device array of FIG. 1. Referring to FIG. 2, the pixel of a conventional active matrix LCD generally comprises an active device 116, a liquid crystal capacitance CLC and a storage capacitance Cst.
Referring to FIGS. 1 and 2, the liquid crystal capacitance CLC is formed by coupling the pixel electrode 118 on the active device array 100 and a common electrode on the color filter (not shown). The storage capacitance Cst is formed by coupling the pixel electrode 118 and the storage capacitance electrode 120, and the storage capacitance Cst is parallel to the liquid crystal capacitance CLC. In addition, the gate G, the source S and the drain D of the active device 116 are electrically connected to the scan line 112, the data line 114 and the pixel electrode 118 of the liquid crystal capacitor CLC, respectively. An overlapping region is formed between the gate G and the drain D of the active device 116, i.e. the area with oblique lines illustrated in FIG. 1. Therefore, a gate-drain parasitic capacitance Cgd is formed between the gate G and the drain D.
Referring to FIG. 1 and FIG. 2 again, the voltage applied to the liquid crystal capacitance CLC commonly keeps a certain relationship with the light transmissive rate of the liquid crystals. Accordingly, a desired frame is displayed by a display if only the voltage applied to the liquid crystal capacitance CLC is modulated according to the desired frame. Nevertheless, the gate-drain parasitic capacitance Cgd is formed, and thus the voltage maintained in the liquid crystal capacitance CLC is varied with the signal change of the data line 114. Such a voltage variation is called feed-through voltage ΔVp and is expressed as formula (1):
                              Δ          ⁢                                          ⁢                      V            p                          =                                            C              gd                                                      C                gd                            +                              C                st                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            g                                              (        1        )            wherein ΔVg indicates an amplitude of a pulse voltage applied on the scan line 112.
In the current manufacturing process of the active device array, the displacement error during movements of the machine would cause nonconformity among the positions of each element. Particularly, when the area of the overlapping region between the gate G and the drain D of the active device 116 such as the area with oblique lines shown in FIG. 1 varies, the gate-drain parasitic capacitance Cgd is changed. Accordingly, the feed-through voltage ΔVp of each pixel 100 in a pair is different from each other, and uneven display brightness during display is generated.